Integrated circuit memory devices generally include memory arrays containing a large number of memory cells for storing data. It is important in producing such memory devices to test writing data to and reading data from the memory cells to determine whether or not there are defective memory cells in the memory device. Conventional processes for testing the memory cells of an integrated circuit memory device can be time consuming because of the vast number of memory cells that need to be tested. Such conventional testing processes include writing data to the memory cells, reading data from the memory cells and checking whether the data read is the same as the data written. In general, one row of memory cells for the memory array can be tested by each read. Because of the time required, it is desirable to increase the speed with which memory cells can be tested during test mode. An architecture for increasing this speed is disclosed by U.S. Pat. No. 5,305,266, issued to Rountree and entitled "High Speed Parallel Test Architecture".